US adds Chinese RISC-V player that TSMC suspected of helping build Huawei GPUs to risky company register
Chinese chip designer Sophgo, a suspected supplier of AI silicon to Huawei, has been added to the USA’s “Entity List” of orgs ...
The Register on MSN9d
Chinese RISC-V project teases 2025 debut of freely licensed advanced chip design
Third-gen Xiangshan may be close to performance of Arm’s made-for-HPC Neoverse 2 A key figure in in China’s drive to develop ...
Hackaday6y
A RISC-V That The Rest Of Us Can Understand
There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs ...
Design-Reuse5y
Extending RISC-V ISA With a Custom Instruction Set Extension
RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
The Risc-V architecture that can shape the future of computing
Open source software rightly gets a lot of attention; open source hardware has its part to play too. One development drawing increasing attention in both technical and executive circles is RISC-V, ...
Open source alternative to x86 and Arm could take off in 2025
The prolific x86 and Arm architectures might soon have another contender to deal with as RISC-V adoption rises.
Hackaday1y
Debian Officially Adds RISC-V Support
The only problem with ARM is that it’s licensed, so if you want to go even further down the open-source path the RISC-V instruction set is the next logical step. Now at least one mainline Linux ...
Design-Reuse4y
Creating Domain Specific Processors Using Custom RISC-V ISA Instructions
A recent catalyst for creating domain-specific processors has been the RISC-V ISA (Instruction Set Architecture). Since the usage of the ISA is open and royalty-free, it is an attractive basis on ...
Electronic Design10d
Multicore RISC-V Designs for Smart Automotive Apps
The MIPS Coherence Manager and shared virtual memory (SVM) use an AMBA ACE interface to tie the RISC-V clusters and the I/O coherence unit (IOCU). The manager supports up to eight units, which usually ...
The Register on MSN2mon
RISC-V reaches milestone with RVA23 profile ratification
Comment The ratification of the RVA23 profile for RISC-V marks a monumental moment for the architecture, and anyone who's ...
Semiconductor Engineering2y
RISC-V Pushes Into The Mainstream
“There’s a standard, but there isn’t just one provider. What’s different is that RISC-V uses a modular approach. There is a base set of 47 instructions, and you add whatever extensions you need for ...
Semiconductor Engineering2y
RISC-V decoupled Vector Processing Unit (VPU) For HPC
“The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...