RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...

The only problem with ARM is that it’s licensed, so if you want to go even further down the open-source path the RISC-V instruction set is the next logical step. Now at least one mainline Linux ...

A key figure in in China’s drive to develop processors based on the RISC-V instruction set architecture has said the project will deliver in 2025, perhaps with a design that could be a ...

Chinese chip designer Sophgo, a suspected supplier of AI silicon to Huawei, has been added to the USA’s “Entity List” of orgs ...

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs ...

Benchmarking tool Geekbench has been updated to version 6.4, seeing added support for RISC-V Vector Extensions and Arm Scalable Matrix Extensions.

What might help people migrate to a more modern processor architecture? RISC-V defines a 32-bit processor instruction set architecture (ISA) that is open source and free to be implemented in any ...

That’s thanks to RISC-V (pronounced “risk five”), an open instruction set architecture used in customized processors for a range of applications. Framework plans to launch a laptop ...

RISC-V is an open ISA (Instruction Set Architecture) that defines the boundary between hardware of the processor design and the software that it will execute, such as operating systems and application ...

Vaishnaw said the most sophisticated of India's initial semiconductors will be built on a 28nm process. The world's most advanced chipmakers are currently working on 2nm processes. However, plenty of ...

Comment The ratification of the RVA23 profile for RISC-V marks a monumental moment for the architecture, and anyone who's ...